1. Field of the Disclosure
The present disclosure relates to a flat panel display device, and more particularly, to a liquid crystal display (LCD) device with a reduced bezel size and an enhanced aesthetic design appearance.
2. Discussion of the Related Art
With the advance of various portable electronic devices such as mobile terminals and notebook computers, the demand for flat panel display devices applied to the portable electronic devices is increasing.
Liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission display (FED) devices, organic light emitting diode (OLED) display devices, etc. are developed as flat panel display devices.
In such FPD devices, the LCD devices are being continuously expanded in application field because the LCD devices are easily manufactured due to the advance of manufacturing technology and realize drivability of a driver, low power consumption, a high-quality image, and a large screen.
FIG. 1 is a view schematically illustrating a related art LCD device, and FIG. 2 is a view schematically illustrating a pixel structure of the related art LCD device.
Referring to FIGS. 1 and 2, the related art LCD device includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix type, a driving circuit unit that drives the liquid crystal panel, a backlight unit (not shown) that supplies light to the liquid crystal panel, and a bezel (not shown) that is formed to surround the liquid crystal panel and the driving circuit unit.
The liquid crystal panel includes a lower substrate (TFT array substrate) in which the plurality of pixels and a plurality of lines for driving the pixels are provided, an upper substrate (color filter array substrate) in which a plurality of color filters and a plurality of black matrixes are formed, and a liquid crystal layer disposed between the two substrates.
A plurality of gate lines and a plurality of data lines are formed to intersect each other in the lower substrate of the liquid crystal panel, and the plurality of pixels are respectively formed in a plurality of areas in which the gate lines and the data lines intersect each other. A thin film transistor (TFT), a switching element, is formed in each of the pixels, and a pixel electrode and a common electrode for applying an electric field are formed in each of the pixels.
The liquid crystal panel includes a display area 10 that displays an image and a non-display area that cannot display an image.
A data driver 40 is connected to an upper non-display area of the liquid crystal panel. A pad area, in which a plurality of pads receiving external signals for driving the respective pixels are provided, is formed in an outer non-display area of the lower substrate of the liquid crystal panel, and a link line that links a corresponding pad to a corresponding TFT and electrode is formed in plurality.
FIG. 3 is a sectional view illustrating the non-display area of the liquid crystal panel of the related art.
Referring to FIG. 3, a seal 30 is formed in an outer portion (i.e., non-display area) of an active area in which the plurality of pixels are formed, and the upper substrate 1 and the lower substrate 2 are coupled to each other with the seal 30.
A gate-in panel (GIP) type, in which a built-in shift register is disposed in the lower substrate 2, is applied for reducing the manufacturing cost of the LCD device due to the driving circuit unit adhered to the liquid crystal panel and reducing a volume and a weight. By disposing a gate driver in each of left and right non-display areas of the liquid crystal panel in the GIP type, the pad area and link lines for applying signals to the respective gate lines of the liquid crystal panel are removed.
The gate driver and the data driver receive different driving signals from a timing controller mounted on a printed circuit board (PCB) 50 and receive a driving voltage supplied from a power supply to thereby be driven.
The GIP type gate driver is disposed in each of the left and right non-display areas of the lower substrate 2. In FIG. 3, only the gate driver disposed at a left side of the lower substrate 2 is illustrated.
The GIP type gate driver includes a common voltage link area 22 receiving a common voltage (Vcom), a ground (GND) link area 24, and a shift register logic area 26 that generates a scan signal for turning on the TFTs of the liquid crystal panel.
Comparing with a type in which a gate driver manufactured as a separate chip is connected to the liquid crystal panel, the manufacturing cost of the LCD device can be reduced by applying the GIP type gate driver, and a volume and a weight can be reduced. However, bezel sizes of the left and right sides of the liquid crystal panel increase.
As illustrated in FIG. 3, the ground link area 24 overlaps the seal 30, for increasing a bezel size. However, the common voltage link area 22 is formed to have a width of about 1 mm, and the shift register logic area 26 of the GIP type gate driver is formed to have a width of 5 mm to 6 mm. For this reason, a left bezel width and a right bezel width are formed at 7 mm to 8 mm, and thus, there is a limitation in reducing a size, causing a reduction in an aesthetic design appearance.
In the GIP type, there is a limitation in decreasing a width of each line and an interval between adjacent lines to a certain level or less, and thus, there is a difficulty in realizing a narrow bezel. When the width of each line and the interval between the adjacent lines are reduced for decreasing a bezel size, a line resistance increases, and thus, a signal is distorted and the shift register logic malfunctions. Especially, in the GIP type, since it is impossible to remove lines, it is difficult to realize an ideal narrow bezel, and moreover, it is impossible to realize a borderless panel.
To solve the problems, a structure was proposed in which the TFT array substrate and the color filter array substrate are switched in disposed position, and the TFT array substrate is disposed at an upper side. However, external light is reflected by a plurality of lines formed in the TFT array substrate, causing a reduction in visibility of an image.